[sdiy] minimum delay calculations

[Tom Wiltshire]

On 15 Dec 2006, at 02:11, Dave Manley wrote:

> Fernando de Izuzquiza wrote:
>> Revisiting the Hammer archive and reviewing the Craig Anderton 
>> Flanger design I see it's clock can run from 25kHz to 5MHz.
>> How to calculate the minimum delay time obtainable at 5MHz?
>> I'd like to have a ~10us to ~10ms delay, voltage controllable.
>> http://hammer.ampage.org/files/Device1-9.PDF
>
> That circuit configures the device for a 512 stage delay.
>
> 25kHz = 40uS, so the delay is 512 * 40 uS = 20mS max delay.
> 5MHz = 2uS, giving 100uS min delay.
>
> Note the one spec I saw for the SAD-1024 spec'd a max clock of 1.5MHz, 
> so that min delay is probably not possible.  If you try to overclock 
> it make sure it doesn't get too hot.
>
> Here's the datasheet for the part:
> http://www.synthdiy.com/files/2003/SAD512-1024.pdf
>
> -Dave (wondering if Harry can resist posting a comment about BBDs)


I have to agree with Dave. I've never come across a BBD that you can 
clock fast enough to get close to the sort of times you're talking 
about. I've mainly played with the MN series chips. Usually a couple of 
mS is about as fast as you can get it before there isn't sufficient 
time for one bucket to fill from the last - you've got a CMOS switch 
resistance and a capacitor giving you an RC time constant that won't 
change however fast you clock it.

I've occasionally wondered about building a through-zero flanger by 
simply delaying the 'straight' signal by 3 or 4 mS. The other channel 
can then be delayed relative to this by a much smaller amount. Perhaps 
this could help you?



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