SV: Re: SV: Re: [sdiy] BBD clock circuit

[JH.]

>Who said it was open?
>This is straight out of the SG3525 data sheet:
>
>DUAL SOURCE/SINK OUTPUT DRIVERS

Hey, you are right!
http://pdf1.alldatasheet.com/datasheet-pdf/view/5632/MOTOROLA/SG3525.html
shows two source/sink outputs.

I could *swear* the datasheet Google came up with yesterday had only
a single transistor per output. So I stand corrected.

No, wait: yesterday, in your first mail, you said SG2524, and I had looked
up
that one, and - surprise - it has single transistors. :)
http://pdf1.alldatasheet.com/datasheet-pdf/view/23559/STMICROELECTRONICS/SG2524.html

> So where is the problem?

No problem at all. I appreciate to learn about new options for BBD drivers.

> idea is the dead band adjustment
> for wich i dont understand why Juergen needs it?

You don't actually need a deadband. You want to avoid any overlap of the
clock signals,
though. Now with heavy capacitive loading (ca. 2.5nF for a MN3005), rise and
fall times
of the clock are increased, and you get some overlap. What makes it worse is
that the
BBD chips are no CMOS devices: The switchich threshold is not in the middle
between
the supply voltage and GND, but very close to the positive side. (i.e. to
GND, if you
supply the BBD with a negative voltage.) So you create a deadband for the
unloaded
clock, a gap which just closes when the BBD is connected. You adjust is such
that
the crossing of rising edge and falling edge of the complementary clock
signals accurs
approx. 10% down from the positive side of the supply.

JH.