[sdiy] Updated Schematics of Rene/Wasp Hybrid

[harry bissell]

Aaron Lanterman wrote:
>
> Harry, thanks so much for your feedback!
don't mention it... all in a day's surfing...

> Ah! That makes sense. When I saw it the other day they were confused 
> about
> why they weren't getting any variation as the turned the resonance pot -
> maybe they essentially have just a one-pole filter going.
One pole or no pole, who knows. If possible in this case (and it ~is~ 
possible
in this case...)  isolate the resonance amp. Feed it a signal, look at 
the output and
see if it is doing what you expect, or want...

>> it will never get enough current to do so... you are correct. you may
>> not guarantee the polarity as shown.  I'd use a NP electrolytic in this
>> type of case. And into the non-inverting input of the TL074 (wrong, as
>> above) the input impedance will be VERY high at that point. Suppose you
>> use a 1M bias resistor to satisfy the input bias current requirements...
>> that is an RC of 47uF and 1M ... a very low frequency indeed.
> will ever blow up? You can 'throw' it in and it will not explode because
>
>> Probably a much smaller cap would suffice... and be easier to get in a
>> NP lytic or even film ???
>
> Interesting. I know they Kai Chi and Sean a 47 uF polarized since that's
> what it looks like in Rene's schematic (one side is white and the other
> black); can we guarantee correct polarity in Rene's schematic? How?
imho, no you cannot guarantee it. OTOH you can probably assume that 
there is no
'net' DC that will cause a real charge either way.

This gets to be a philosophical discussion.  Although the cap will not 
likely fail, its operation
is not guaranteed by design either. I can say that many many many 
designers have gotten away
with it. OTOH I think this is why the advice "replace all the 
electrolytic caps" comes up so
often in vintage electronics.  At small signal levels a lot of folk 
don't care that the polarity
could be reversed...
>
>>> There's a 10 mufarad cap that looks polarized due to the "+." One side 
> of
>>> the cap is at virtual ground. The other - well, how it looks like the
>>> voltage on the other side swings both ways - how come this doesn't blow
>>> up?
>
>> where is it ??? or is the value different ???
>
> http://rubidium.dyndns.org/~magnus/synths/companies/buchla/Buchla_2590_3_200.jpg 
>
>
>
> If you're looking at it in proper landscape, you'll see the 10 mufd as
> part of the final filter/clipper; the + makes me think it must be
> polarized. But it looks to me like the voltage at the + side could swing
> either way.
yes it can swing either way. This is a big 'modular' desing problem... 
sometimes
people can put DC levels into modules, of either polarity. The NP 
electrolytic
can handle it for sure... otherwise... ????
>
>> I don't know what they mean by 'frequency clamping' ... does that mean
>> that the filter does not tune and stays at 16KHz cutoff...
>
> I'm not sure - Kai Chi, Sean, could you give more details.
>
>> I don't see the 'sallen key' archetecture clearly here...R5 and R10 make
>> these stages look more like single pole OTA stages... with unusual
>> feedback.
>
> Usually R5 would go back to the - input of U1, but since the inverter
> inverts, we need to put it into the + terminal, right? (That's what I 
> told
> them to do, but maybe I'm missing something. Let me look at R10... let's
> see... what comes out of buffer of A1 in Rene's schematic winds ups
> inverted, so if it goes into the + pin of O2 on Rene's schematic, I
> thought it should go into the - pin of U2 on the students' schematic to
> cancel the inverstion... similarly... the feedback from buffer A2 in
> Rene's schematic goes to the - terminal of the 3080, but, since the
> inverter buffer in the student schematic inverts, I had them take it to
> the + terminal.
>
> I'm probably confused though. Help us Jedi Master Harry!
LOL.  You would be looking for Yoda, young Skywalker.  I am merely some guy
who slept with your sister Leia. :^P

I expect to see... two resistors whose er... resistance can be varied, 
and two caps
(fixed) and a high impedance buffer / amplifier with some provision for 
changing gain
if you want to change "Q".

I think that the local feedback around the OTA / buffer stages makes the 
circuit something
else. My math chops are not good enough to say exactly what that is, but 
I'm suspicious...

So usually in these cases I draw it in a simulation program and see what 
happens.

Like the King of all Jedi (Bob Pease)... I do not blindly trust 
simulation. It ~can~ and often is
wrong.  Somtimes it will correct you if you make a dumb mistake, 
sometimes you will correct it.
Other times you will agree. 

I use simulation because I ~can~ use it at work. Instead of an 
industrial control, I might be checking out someone's VCF :^P

I have had circuits that Spice said would NOT work, that do just fine. 
It does not handle mixed
models well, at all.  When you get into 4069 buffers they are really a 
MOS transistor array
NOT a digital gate, anymore. The distinction is important... I got 
burned badly doing an FPGA
design where I assumed that the logic elements would work just like the 
discrete counterparts
(ie asyncronous design)  oops... my bad :^)
>
>> If I have some time I'll try and simulate this circuit.  Are your
>> students using any simulation programs ???  If so they can make an OTA
>> model from discrete transistors by copying the 3080 schematic... but use
>> DIODE connected transistors (b-e junction) that match the other
>> transistors. do NOT use the 'diode' model
>
> I don't think they are on this one. Not all the students in the class 
> have
> seen SPICE in their courses yet, and mastering SPICE takes some time, 
> so I
> didn't want to make using it a requirement. Many of the students who are
> comfortable with it are using SPICE.
Amen brother.   It took me more than six months to get comfortable with 
the simulation
at all... and maybe a year to eighteen months to be proficient.  I do 
use it at work... just as
a sanity / insanity check. ALWAYS I compare the simulation and the real 
world... and play with
the models to learn what real parameter I have failed to simulate :^P

I has a circuit that I inherited... with some RC networks that seemed to 
do nothing. Until I added
real world inductance to the power supply.  In the real world they 
prevent the circuit from broadcasting on the middle of TV channel three :^P
>
> That's a good piece of advice on the OTA model - some of my students were
> complaining about not having a model for the OTA chips.
>
I have used it extensively and its a good match. I used 2N3904 / 3906 
transistors. Probably
OK ihmo.

The LM13600 / 13700 is a macromodel, not a physical simualation... it 
works OK but is
not super-accurate.  I made a CA3280 model with the physical simulation, 
but have not validated
it. It looks OK but I don't have the practical feedback yet to see if it 
is valid. It does seem to work
OK.

H^) harry