[sdiy] Digital VCO

[Eric Brombaugh]

I wish I had enough processor cycles to implement dithering in this 
application. The PSoC 9-bit DAC is rather quirky since it is implemented 
as 2 blocks of switched cap ratiometric charge-steering. The 9-bit value 
needs to be split into 6-bit and 3-bit sections, and doing that with the 
limited available bit manipulation instructions takes too much time, so 
the sine table is stored pre-split. About all I have time for in my ISR 
is to update the current DAC values, increment the DDS phase and look up 
and save the DAC values for the next cycle. This takes about 60% of the 
overall processor bandwidth. The rest is taken up in servicing the ADC 
and computing the exponential frequency.

Note that some enterprising individual has an appnote on how to 
implement an 11-bit DAC, but that technique requires hacking the XML 
which defines the PSoC user modules, as well as run-time calibration to 
ensure monotonicity. I think I'll save that for later. Much later. :-P

For an LFO the sampling rate could be reduced significantly which would 
allow more time for fancy-pants DSP stuff. :)

Eric


ASSI wrote:
> You can increase the phase resolution, improve the interpolation and 
> dither the output very easily in this case. In fact a relatively easy 
> 2-bit or 3-bit dither could likely improve the apparent resolution in 
> Eric's current design for audio frequencies. For an LFO design it may be 
> possible to replace the wave LUT with a table of Walsh coefficients.
>