[sdiy] CMOS clock inputs.

[René Schmitz]

Hi Dave,

Dave Kendall wrote:

> The clock advances on a Low-High transition, so I guess it should be
> connected between CLK and GND. What would be a good value to start with?
> supply is 0V +15V.

I would add a transistor with its emitter to GND, and a collector 
resistor in the neighbourhood of 4.7k to 15V. Then also a resistor at 
the base of 4.7k, and a diode from base to GND with the anode connected 
towards GND. This effectively protects the CMOS inputs, and also you 
don't need a full 15V swing to clock it anymore. The transistor has 
enough gain so that you can use audio signals. But you need to make up 
for the inversion in your case. (A second stage like that would do.)

> I've had a look in some text books, and an unconnected TTL output floats up
> to HIGH, but it doesn't mention what CMOS inputs and outputs do...

CMOS does float up where ever the leakage takes it. It is "forbidden" to 
have them floating.

Cheers,
  René

-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159