[sdiy] Trace width and via diameter/hole size

[Harry Bissell Jr]

Hi Bert


> I'm using approx. 12 mils for power traces and 8
> mils for 
> signals. According to the ULP's in eagle the 12 mil
> trace 
> Should be able to handle close to 1A? Is my 12 mils
> for 
> Power to narrow? The highest current in the system
> will 
> Be around 890mA. 

12 mils is pretty small for power traces IMHO. I'd
make them bigger. Its not a matter of current carrying
capacity, its a matter of voltage drop. You do not
want
any measurable voltage drop in the supply traces... or
you will be coupling parts of the circuit together you
did not intend.
> 
> > Vias usually have better current carrying capacity
> than runs. 
> > The whole inner barrel is copper plated.
> 
> Mm... The pcb fab I'm using in Belgium seemed to
> have a choice
> Between filling vias and not filling them.. So I
> should ask 
> Them to fill them? Last time my board arrived it
> didn't have 
> The vias filled. 

I did not write that clearly. Most vias are not
filled... they are plated on the inside surface of the
barrel. These days some companies are specifying
filled vias, which have the holes completely filled.
This can be helpful for keeping the soldermask out of
the holes
and in most cases, these are TINY TINY (is that an
oxymoron - tiny in capital letters ?) vias.

Ther are NON-PLATED vias as well as Paul Perry pointed
out.

I'd use PTH (not filled) for most boards

H^) harry



> 
> Thanks !
> bert
> 
>