[sdiy] Staircase Generator: 4 bits but 8 steps?

[Roy J. Tellason]

On Tuesday 06 September 2005 04:22 pm, xamboldt wrote:
> I sent this message yesterday, but so far it hasn't shown up on the list -
> apologies if you get it twice...
>
>
> Hi Everyone,
>
> I breadboarded an EFM staircase generator. It uses a 74LS93 to generate the
> 4 binary digits, but I'm only hearing 8 steps on the staircase. It's a
> 4-bit device, and 4 bits is 16 steps, right? Shouldn't there be 16 steps on
> the staircase? From what I understand, the D/A section is pretty standard -
> see the asciimatic below:
>
>
>          20K
> Bit 3 /\/\/\/\------------to opamp buffer
>               /
>               \10K
>               /
>          20K  \
> Bit 2 /\/\/\/\-
>               /
>               \10K
>               /
>          20K  \
> Bit 1 /\/\/\/\-
>               /
>               \10K
>               /
>          20K  \
> Bit 0 /\/\/\/\-
>               /
>               \20K
>               /
>               \
>
>              GND
>
>
> At first I thought maybe that Bit 3 wasn't getting through, but according
> to my continuity tester, it's hooked up. Yes, pins 12 and 1 are connected
> to utilize the 74LS93 as a full 4-bit counter.

And you're driving this directly from the output of the counter?  What I would 
do is to take a DIPswitch (or something) and apply the states to the inputs 
of that network one at a time,  and see what you get at the output.

TTL is _not_ very good at sourcing current,  much better at sinking it,  so I 
would tend to build something like this with one end tied to +Vcc and some 
sort of a buffer or other open-collector part pulling the inputs to ground,  
for whatever thats' worth...


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