[sdiy] FET for VCO cap discharge

[JH.]

> >If you put a slight forward bias on the gate-source junction, the drain
> >current can increase beyond Idss... any possibility that this could be
> >happening during the sawtooth reset?
> >Regards, Mike
>
> Yes, definitely.  The comparitor output is connected directly to the gate
> in this design.  (Always makes me nervous, but that's how Terry did
> it.)

Wait a minute - I thought that's an open collector comparator, so the
maximum voltage would be where your collector resistor goes, i.e.
GND ? So the Gate capacitance is discharded by 3.2kOhm to GND
(FET turn on), and discharged by the open collector to the negative rail
(FET turn off, immediate start of new ramp)

JH.