[sdiy] FET for VCO cap discharge

[Ian Fritz]

At 03:06 AM 10/23/05, JH. wrote:
>No, in fact the circuit keeps the gate at GND level

Actually, it's the source that's at virtual ground.

>  while the drain
>is up at 4V (and goes down to 0V)

Right.

>, so it even need s a FET
>with a threshold voltage larger than 4V.

During the ramp the gate is near the negative rail, so pinchoff voltage is 
not a limitation (unless it is over 10V).

>I guess the amplitude of 4V in the core has been chosen just because
>thats the minimum spec'ed threshold voltage of the 4391.

Actually, just to reduce the swing of the flyback just a bit.  :-)

   Ian