[sdiy] FET for VCO cap discharge

[Ian Fritz]

At 04:03 PM 10/22/05, Mike I. wrote:
>If you put a slight forward bias on the gate-source junction, the drain
>current can increase beyond Idss... any possibility that this could be
>happening during the sawtooth reset?
>Regards, Mike

Yes, definitely.  The comparitor output is connected directly to the gate 
in this design.  (Always makes me nervous, but that's how Terry did 
it.)  But the spec sheet only gives the zero-bias number.  And it doesn't 
give R_ds.  The puzzle is why the BF256C is better than the 2N4391.

   Ian