[sdiy] FET for VCO cap discharge

[JH.]

Hi Mike,

> If you put a slight forward bias on the gate-source junction, the drain
> current can increase beyond Idss... any possibility that this could be
> happening during the sawtooth reset?

http://home.earthlink.net/~ijfritz/sy_cir2.htm

No, in fact the circuit keeps the gate at GND level while the drain
is up at 4V (and goes down to 0V), so it even need s a FET
with a threshold voltage larger than 4V.
I guess the amplitude of 4V in the core has been chosen just because
thats the minimum spec'ed threshold voltage of the 4391.

JH.