[sdiy] Some OTA questions

[James Patchell]

Generally, Id is held constant during normal use, as Id will also determine 
the maximum input voltage.  There are times when making Id variable can be 
useful.

The sample and hold I did...

http://www.oldcrows.net/~patchell/archives/ca3280_9.html

you would connect the - input of the CA3280 back to Vo and apply the 
voltage you wanted to sample to the + input.  When in sample mode (Sample 
input high), the circuit will servo until the + and - input of the CA3280 
is zero, making Vo equal to Vin.  The rate that this will happen at will be 
determined by the value of Iabc, Vo will slew at the product of Iabc *Ch.

In the sample and hold, Id is set to zero, since no input linearization is 
required.  The same circuit will also work with the CA3080 as well.  The 
sample and hold will also work with a FET follower as well...the CA3280 
will have to do a bit more work since it will have to servo out the 
Gate-Source voltage of whatever FET is used.

Anyway...hope this helps a bit...

At 10:06 PM 11/26/2005 -0500, Jeff Farr wrote:
>Jim, thanks, those are perfect.
>
>"Basically Id will allow you to use a higher level signal in"
>
>This will improve it's usefulness as a VCR as well, right?  Looks like
>I've got some breadbording to do..  I'm still not clear on the
>relationship between Vdiff and Iout in the S&H circuit, it still seems
>to me that if Vdiff is enough for one of the transistors in the first
>mirror to be all the way open (which happens at a fairly low voltage)
>then the output current is largely unaffected by the input voltage and
>is really just Ic.  I'm not shure how the circuit maintains a direct
>relationship between Vdiff and Vcap and there is no circuitry after
>the FET to re-scale Vcap so that it fits with Vdiff.. Perhaps I'm
>looking to much into it, or too little into it.

         -Jim
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