SV: Re: [sdiy] Making my own Signal Processing in VHDL

[karl dalen]

--- James Patchell <patchell at cox.net> skrev:

> That sounds like a fun project...which FPGA are you prototyping with (not 
> that it really matters...)...
> 
> I still have hope of someday completing an FPGA based synthesizer...
> 
> At 07:54 PM 11/12/2005 -0500, Sumanth Peddamatham wrote:
> >Hello All,
> >
> >I'm designing a signal processing chip intended for use in a low-cost
> >guitar pedal.  If I come up with an interesting enough design, I might
> >even have the chance to have it fabbed into an ASIC!
> >
> >Right now, I've written the blocks necessary to interface with a
> >16-bit ADC and a 16-bit DAC, the AD977 and MAX541, respectively, and
> >have prototyped them on an FPGA.

Here's my five cent:

I think thats a "tiny" misstake, its much
better if you do a CODEC type of interface.

Codecs are way cheaper then sparate 16 bit ADC and DACs.
And not only that, with a standard codec interface you 
can apply whatever codec you can get, i considder that 
as a significant point in design!

Particularely if you are going to fabbit later!

> >The three effects I'm working on right now are Tremolo,
> >Vibrato/Delay/Chorus, and a basic Distortion.  The Tremolo uses a LFO
> >to vary the amplitude of input samples.  The Vibrato/Delay/Chorus
> >block uses a 4000 tap, 16-bit register to give me 50ms of buffering at
> >a 80 KHz sampling rate.

Equals a tap a ram bit?

Reg
KD