[sdiy] Making my own Signal Processing in VHDL

[Sumanth Peddamatham]

Hello All,

I'm designing a signal processing chip intended for use in a low-cost
guitar pedal.  If I come up with an interesting enough design, I might
even have the chance to have it fabbed into an ASIC!

Right now, I've written the blocks necessary to interface with a
16-bit ADC and a 16-bit DAC, the AD977 and MAX541, respectively, and
have prototyped them on an FPGA.

The three effects I'm working on right now are Tremolo,
Vibrato/Delay/Chorus, and a basic Distortion.  The Tremolo uses a LFO
to vary the amplitude of input samples.  The Vibrato/Delay/Chorus
block uses a 4000 tap, 16-bit register to give me 50ms of buffering at
a 80 KHz sampling rate.  The Distortion block is a basic peak and
trough clipper.  I hear that an asymmetric distortion is more pleasing
than a symmetric distortion.  Why is this?

I have a proposal and initial design which I'll put up on my
university account soon.

Does anyone have any ideas or insights they would like to share?

Sorry for the tangential and rambling nature of this post.  I've been
up for 2 1/2 nights working on this project and things are finally
coming together.  I'm totally stoked!


Sumanth P.

ps. I intend to publish all the source code and design notes for the
project when I'm done.