[sdiy] Semi CMOS VCO Update

[Scott Gravenhorst]

I've decided to shelve this one, at least for now.  2 things that I just
didn't like:

1) The ramps don't appear to be straight when a straight edge is held to
the oscope screen.  This will affect linearity.  I don't understand this,
because the same integrator is used in the René Schmitz sawtooth VCO and
that VCO has a nice straight ramp and very good linearity.  I'm not really
sure why the ramps aren't straight with this VCO.

2) The 7.5 volt point created by the inverter gate with it's output and
input connected to the cathode end of the 3 diode string self destructed
during testing.  Too much current, I'm guessing.  After replacing it, I
found that with the diodes not connected, 7.5 volts was nicely maintained.
 As soon as the diode string was connected, the voltage rose to about 9 volts.

I may take this up again at a later time using 10 times less current
through the current mirror and a 10 times smaller integrating capacitor
(.001uF instead of .01uF).  

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