[sdiy] Discrete SSM2040 & Spice

[tomg]

Nope, you're right but it's usually negative and a little less ?? Balance
the
current mirror then offset trim one of the inputs for each cell until it's
perfect.
The reason for zero offset is to minimize pops and clicks that can occur
with fast CV changes. The offset is so small there's really no problem.

Regards
Tom

> Hello
>
> When doing Spice simulations of a discrete SSM2040 filter stage
> (http://www.uni-bonn.de/~uzs159/rs2040.htm), the output appears to have
> some 0.3V DC offset (even though the transistors are perfectly matched).
> I have traced this to the difference in the collector voltages of the
> differential pair (Early effect basically).
>
> Is it really this huge in the real circuit or is my Spice faulty?
> If Spice is right, what is the point of matching the differential pairs
> when Early effect alone causes such huge offset?
>
> Antti
>
> "No boom today. Boom tomorrow. There's always a boom tomorrow"
>    -- Lt. Cmdr. Ivanova