[sdiy] Digital noise generation

[Magnus Danielson]

From: Antti Huovilainen <ajhuovil at cc.hut.fi>
Subject: Re: [sdiy] Digital noise generation
Date: Tue, 8 Mar 2005 18:53:29 +0200 (EET)
Message-ID: <Pine.OSF.4.61.0503081849460.2284 at kosh.hut.fi>

> On Tue, 8 Mar 2005, Magnus Danielson wrote:
> 
> > I assume you meant 200 kHz to 1 MHz.
> 
> Yes.

OK. I'm a bit picky about those things, so I just wanted to make sure.

> > What polynomials did you use?
> > If you dig in the Synth-DIY archive I published a list up to length of 64.
> 
> I tried both N = 23, M = 18 and N = 31, M = 28. Both suffered from the 
> same problem. Strangely, at least N = 23 case sounded okish if FSR was 
> clocked at 44khz.

Your problem is probably due to the aliasing problems and that low clock rates
doesn't sound OK when generated in serial form.

> Repeat time was not a problem for either as I only listened for a few 
> seconds, which was enough to convince me that the result was intolerable.

I beleive you.

> > Did you use a parallelized version?
> > I can help you with that if you need.
> 
> No. What's the difference to normal LFSR?

Instead of generating 1 bit you generate N bits from the same number of state
bits. Also, the state bits is advanced not 1 but N steps in the phase. It's
not very hard to acheive this. I have some VHDL code lying around somewhere
which does this. Just an exercise with XOR gates and simple linear math really.

There is numerous articles on how to make this parallelized in CPUs, where for
instance multiplication can be used.

I can dig deeper into it later tonight if needed.

Cheers,
Magnus - who just recalled that my VHDL code needs attention