[sdiy] My New Project - PCSYNTH

[Scott Gravenhorst]

After completing some testing, I have decided to move forward with PCSYNTH,
my new project which was springboarded by AVRSYN.  

My design will use an LPT port to send data to a DAC.  I will initially use
an AMD 5x86-133 processor for this.

The main concern raised here on SDIY was that the LPT port is too slow to
produce output at 44 KHz update rate to the DAC.  Today, I wrote a tight
loop to see just how bad the situation is.  What I saw on the scope would
suggest that a rate of 333 KHz is a more realistic ceiling.

After testing 5 different LPT ports, I noticed that some have very slow
slewing time - and they also have resistors (1K) between the register and
the socket pins as well as a capacitor (probably for EMI reduction) from
the LPT data pin to ground.  Removing these capacitors should drastically
improve the response of these devices.  Looking at the oscope, the rise and
fall looks just like an exponential charge curve as any simple RC circuit
will exhibit.  I am currently using an LPT port that never had the
capacitors and is shows a rise/fall time so fast, I can't accurately
measure it, but it looks around 5 nanoseconds or less.

Much of the amount of time it takes to simply toggle an LPT port bit comes
from the 'out' instruction, it seems to take about 1.5 uS on this CPU. 
However, I had to add 100 16 bit move instructions before I saw any
lengthening of the time which indicates that while the out instruction is
slow, the rest of the instruction set seems quite fast.  I believe it will
take 5 out instructions per DAC update, which is 7.5 uS on this CPU.  That
leaves about 14.5 uS for the computation of each new DAC value.  It's not
as good as I wanted, but this is also the slowest machine I have and there
are a few other old ones here that are faster that will be able to do more
with that 14.5 uS (assuming all of them have slow out instructions).

My first experiment will be using an 8 bit DAC, and if this is successful,
I will see about a 12 or 16 bit DAC implementation.  The DCOs will use 32
bit phase accumulators.  The PCSYNTH program will be written in X86
assembly language.

Obviously, this architecture is not perfect for this purpose, but this is
equipment I have laying around, begging for something like this.

While I like the AVRSYN design, it's running "to the wall" (95% according
to Jarek) to support only 2 DCOs.  I am interested in more than 2 sound
sources, as well as doing wave table lookup for waveforms like sine and
user created waves.

My thanks and gratitude to Phillip Gallo for his encouragement and words of
wisdom in this.

I will probably start a web page for this project, but at this point it's
too early.



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-- Scott Gravenhorst | LegoManiac / Lego Trains / RIS 1.5
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