[sdiy] Decode between Decay phase and Sustain?

[Oakley Sound]

> Has anyone seen a clever way to generate a logic bit at the end of the 
> the decay phase in an ADSR?

Technically there is no separate state in the sustain mode of a 
exponential ADSR. The Sustain simply sets the voltage to which the decay 
is falling towards. So the decay mode is still valid until the release is 
activated. The sustain isn't an event in time, but a controllable level.

However, one could say though that the sustain period starts when the 
decay is percieved to have stopped, eg. 10RC.

In a linear ADSR then there will be a point by which the timing cap 
reaches the sustain period. So at least that does have some sort of 
definition.

In either case, a simple comparator monitoring the cap voltage would 
probably be of some use.

Of late though, people keep on telling me that they could do all this 
with a PIC and a 14-bit DAC. But on that I know nothing .... :-)

Tony

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