[sdiy] 4514 w/4516

[Phil Harbison]

Tom Arnold wrote:
> I'm looking at the TI datasheet downloaded from alldatasheet.co.kr.
> Page 5 of the PDF labeled 3-253, Figure 16.
> 
> If you look at the CARRY OUT line, when it counts to 0 (colume 21)
> there is a definate lag past the clock leading edge.

What column 21 illustrates is the carry propagation from
CARRY-IN to CARRY-OUT. If you are counting down and reach
zero and CARRY-IN is low, CARRY-OUT will go low, but if
CARRY-IN then goes high, CARRY-OUT also goes high because
carry should only be propagated if this stage is at the
terminal count (0-down or 15-up) and CARRY-IN is low from
the less significant stage.

Ordinarily, CARRY-IN would be tied low on the least signi-
ficant stage since that stage should always count on every
clock cycle *unless* you choose to use CARRY-IN as a count
enable control. This diagram illustrates the count enable
usage in column 21. CARRY-OUT will transition immediately
after the clock edge when CARRY-IN is low and the counter
reaches terminal count; however, unlike the Q ouputs which
are purely synchronous, a change in CARRY-IN immediately
propagates through to CARRY-OUT.

If you choose to use CARRY-IN as a count enable you should
synchronize it to the clock with a D flip flop, i.e. run
the count enable signal from a front panel switch to the
input of a D flip flop and the output of the flip flop to
the CARRY-IN input of the counter, with both the flip flop
and the counter using the same clock. If you do not synch
the count enable signal, you risk violating the input setup
times of CARRY-IN on all stages.

> My test setup is two 4516's basically wired in parallel except CO -> CI.

This is the correct configuration for synchronous cascading as
described in page 1, paragraph 2 of the data sheet.

  "If the CARRY-IN input is held low, the counter advances up
  or down on eachc positive-going clock transition. Synchronous
  cascading is accomplished by connecting all clock inputs in
  parallel and connecting the CARRY-OUT of a less significant
  stage to the CARRY-IN of the more significant stage."

This is illustrated in Figure 18 on page 6 (parallel clocking).

> I'm only flogging this dead horse because thats what I could See with my
> little LED's hooked up, step 16 -> 17 lagged a tiny but visible amount.

I'm not familiar with your circuit but if you have two 4516's
connected as shown in figure 18 (parallel clocking), the lag
from the clock edge to 00010000 (16) appearing on the output
should be the same as from the clock edge to 0000xxxx (0-15).
At 5VDC, the maximum propagation delay from clock to Q output
is 400 nsec. and the skew from output to output or clock to
clock is probably less than 1/10 of that. The difference can't
possibly be seen by the human eye so there must be some other
problem.