[sdiy] SRAM access

[John Speth]

I think the OE (output enable) simply enables the
device data bus output drivers when it's asserted. 
This permits data bus sharing for multiple devices
without the use of muxes.  SRAMs are static devices
(hence the name) and it imposes no "cycle"
requirements other than meeting setup/hold and access
time requirements

Check your data sheet first but you can hardwire OE
asserted so long as the data bus is not being driven
by another device.

JJS

--- Chris CROSSKEY <chris at crosskey.fslife.co.uk>
wrote:
> I thought you had to cycle the OE after changing the
> address bits....mebbe 
> I'm wrong... don't some have OE/WR-bar (or vice
> versa) plus clock?.... am I 
> geting confused here?
> ----- Original Message ----- 
> From: "Antti Huovilainen" <ajhuovil at cc.hut.fi>
> > Is it possible to tie output enable (OE) high and
> still use common SRAM 
> > chips just by changing address bits?
> >
> > I have checked datasheets for 6264 and 62256 but
> they don't say anything 
> > about that and timing diagrams assume normal
> cpu-like access with OE 
> > strobed after address has been latched.
> >
> > Antti
> >
> > Give a man a fire, and he'll be warm that day,
> > Set him alight and he'll be warm for the rest of
> his life
> > 
> 
> 
> 



		
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