[sdiy] more pitch shifter thoughts

[Scott Gravenhorst]

Magnus Danielson <cfmd at bredband.net> wrote:
>From: Scott Gravenhorst <music.maker at gte.net>
>Subject: Re: [sdiy] more pitch shifter thoughts
>Date: Mon, 10 Jan 2005 10:00:48 -0700
>Message-ID: <200501101800.j0AI0mV10516 at linux6.lan>
>
>> Grant Richter <grichter at asapnet.net> wrote:
>> >You can build one with just a top octave chip and a CD4046. The TOC just
>> >need a high frequency clock phase locked to a reference VCO square wave. A
>> >switch can select the high or low C from the TOC and give and octave above
>> >or an octave below the reference VCO. (IIRC with a 50240)
>> 
>> Being a 4046 PLL kind of guy, I have wondered about stability and tracking
>> when doing this.  I have a PLL module that uses a divide by 12 counter in
>> the loop and it works just fine.  But the MK50240 has a range from divide
>> by 239 to divide by 478.  
>> 
>> What kind of problems, if any, will there be with such large counters?  
>
>Larger dividing ratios will divide the loop gain by the same amount. You need
>to take that in count.
>
>> I would think that proper VCO capacitor selection is important.
>
>Indeed it will. The loop-gain being different for different ratios (/1 being
>refernce for "normal" cases) and thus you end up with basically two troubles,
>that of changed steady-state stability point and that of changed Q-value which
>potentially renders the responce very resonant and thus unstable, beside having
>it providing phase-noise gain at the PLL bandwidth, which is not a good thing
>most of the time.
>
>> Over/undershoot?  
>
>Yes.
>
>> Does a large counter affect lag very much?  
>
>Yes.
>
>> My own circuit has adjustable damping for the loop filter and allows me to
>> adjust it so that frequency changes are so immediate that I do not hear any
>> over/undershoot or lag.  But then, my PLL has only a divide by 12 counter
>> in the loop.
>
>That is a good move. However, by spending a little care will an octave of range
>not be as much of a trouble. The trick is to make the loop-gain change occur
>over a well damped case, so it's loosest end is more or less critically damped.
>It is a bit of numerics but it is fairly simple to do.
>
>There is a bunch of different sources for the calculation, which one are you
>using?

Oh just the simple one for calculating the capacitor value.  I don't have the
details of what that mounted to.

>
>I've been doing multiplications beyond 2000 with no problems, but that was no
>4046 in there. Infact, for some uses the 4046 is so darn bad, and especially
>the charge-pump buissness has better reputation than it should have. Too many
>use it blindly without understanding the issues. 

Like me!  Blindly used or not, I was extremely happy with the result.  It does 5
octave jumps with little more than a chirp.  I drive it only with a VCO output
that presents a signal as large as the 4046 rail to rail voltage.  I used Phase
Comparator II to get the large lock range and prevent locking onto harmonics.

>Let's say I'm not impressed
>when seeing it in action in what proved to be a critical application, where as
>using a much simpler setup locked and just kept going without headaching
>trimings and problems.
>
>OUPS! Now I am 4046-bashin again!

Ah, well, probably my application wouldn't be considered "critical", it only has
to sound good, I don't care too much about problems that don't present
themselves to my ear.  The only reason I soldered it together is that I tested
the design on solderless breadboard and it worked surprisingly well, far better
than I'd hoped.

Thanks for the info.  Again I get an education on this list.

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-- Scott Gravenhorst | LegoManiac / Lego Trains / RIS 1.5
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