[sdiy] "AVR synthesizer"

[James Patchell]

Actually, it would be a fairly trivial matter to get, say, 1024 SVF into a 
Spartan III Fpga consuming very little resources.  You only need one 
multipiler to do all that work, and it won't consume any actual logic 
resources.  You just need the appropriate amount of block, ram, a 
multiplier, and adder (which will use logic), and some glue logic...and you 
have 1024 SVF to do what you want with....

At 09:16 PM 2/16/2005 +0100, Jaroslaw Ziembicki wrote:
>----- Original Message -----
>From: "Rainer Buchty" <rainer at buchty.net>
>To: "Jaroslaw Ziembicki" <aon.912230836 at aon.at>
>
>
> > 1. tmp1=in-XX where XX is either ys (LP) or xs (HP)
> > 2. tmp1=tmp1*KK where KK is either cc (LP) or 1 (HP)
> > 3. tmp2=ys*KK where KK is either 1 (LP) or cc (HP)
> > 4. ys=tmp1+tmp2
>
>Rainer, I meant that a 2nd order variable-state filter would
>consume those 20K gates! A 1st order filter that you are
>describing above would need no more than 3K..5K.
>I managed this without problems during my experiments
>with an Altera chip containing 10K gates.
>
> > That would be my approach... However, the FPGA devel station is not net
> > up yet, so I can't instantly test a VHDL model of the above. But maybe
> > end of this week.
>
>I'm curious...
>
>Regards, Jarek

         -Jim
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