[sdiy] "AVR synthesizer"

[Rainer Buchty]

>By the way - an implementation of such filter in an FPGA would cost
>some 20K gates... Anyone is going to try?

Using an architecture with multipliers and memory cells like Spartan III
or the Virtex series there shouldn't be plenty of logic involved,
basically addressing the x- and y-storage (xs, ys) and cutoff
coefficient (cc) registers for each filter followed by a short
computation pipeline which does

	1. tmp1=in-XX where XX is either ys (LP) or xs (HP)
	2. tmp1=tmp1*KK where KK is either cc (LP) or 1 (HP)
	3. tmp2=ys*KK where KK is either 1 (LP) or cc (HP)
	4. ys=tmp1+tmp2

Results in roughly:
- 3*n*18-bit memory for xs,ys,cc (here probably SelectRAM is preferred)
- log2(n)+2 bits for the state machine (n being the number of filters
  the chip should offer)
- 2x 18 bit registers (multipliers are 18x18 bit signed)
- 2x 18 bit adder (well, one adder, one subtractor)
- 3x multiplexers (which will probably eat up the most space in the
  above design)

One step can be skipped if the filter should not have switchable
characteristic.

That would be my approach... However, the FPGA devel station is not net
up yet, so I can't instantly test a VHDL model of the above. But maybe
end of this week.

Rainer