[sdiy] Xilinx Spartan 3 kits

[Rainer Buchty]

>PS:Vhdl,Verilog,CUPL, it sounds nice but in the end its not the
>easyiest thing to actually get the code right! VHDL has many pitfals!

Every programming language has its pitfalls.

And it's too bad that many (preferrably academic) publications tend to 
introduce VHDL as a "normal" programming language including BNF and 
everything, but not telling the difference between synthesizable and 
behavorial descriptions -- possibly cause some of the authors never did 
a piece of code on their own.

This is probably the hardest part to understand, that you can code VHDL 
which just can't be translated into hardware, like e.g. timed wait 
statements ("wait for 10 ns").

Rainer