[sdiy] Buffering Busses?

[Dave Kendall]

Thanks for the replies guys....

on 28/12/05 13:22, Scott Gravenhorst at music.maker at gte.net wrote:
> I don't know anything about the VCO3D, I assume it is a dual VCO?  You say
> that one is "fine", did you try using just the "bad" VCO alone and measure the
> pitch CV both with and without?  If the CV changes when one VCO is plugged
> in, but doesn't change when the other is plugged in, the "bad" VCO has a low
> impedance input (a shunting resistance to ground?) or perhaps something very
> bizarre happening with the buffer.

Good idea. The VCO3D is a dual VCO. I'll try one and/or the other OSC
straight off the MIDI2CV, and then try again with the voltage follower - see
if there's any difference.

> .... a VCO pitch CV input should probably be a lot higher than 10K.
 The  1V/oct input for each VCO goes via a 50K trimmer and a series 22K
resistor to a summing node, that also receives the Pitch mod input via a
100K resistor, a 50K INITIAL trimpot followed by a 47K resistor, and the
coarse and fine tune pots which are both 50K pots connected to +V and -V
with wipers going via series 1M and 330K resistors respectively. This
summing node connects to the base of one transistor in a CA3046 (part of the
expo pair?...) and also goes via a 1K tempco to GND....

Some designs I've seen have standardised on 100K input resistors for all
inputs.....I'm a bit confused by the different values in the VCO3D...

>>I got a tracking error when connecting both oscillators in an EFM VCO3D to
>>the 1V/oct CV from the Paia.
>This error shouldn't happen if you are running the VCOs direct from (for
>example) pin 1 of IC11:A.  Do you have some kind of LAG or other CV
>processor circuit in between?

No - the 1V/oct was planned to go straight to a voltage follower, then to
the buss.
There IS a lag circuit on the Pitch Wheel output, but that also goes through
an offset/scaler with a multiturn trimmer so *hopefully* that should be
trimmable.
Maybe I should put that output through a voltage follower too?

>Clocks could be more of a problem because it depends on the input
>characteristics of the clock receiver - i.e. whether it's a digital or
>analogue circuit. CMOS shouldn't mind being driven by an op-amp because
>it's high-impedance anyway, although it's traditional to have a 100k
>pull-up/pull-down resistor on the input so that it doesn't float when it's
>not connected to anything.TTL would be a problem, but I'd guess you're not
>using that.
The circuits receiving clock are either CGS modules, most of which use 100K
input resistors, or the Blacet MidiSync IC circuit which I'm about to
breadboard as per the Blacet App notes. The EFM VC RADSRS that would receive
the gate will probably use a CGS design input buffer, so should be OK
too?....

>>(I REALLY need to get that Horowitz and Hill book.....
>
>Definitely recommended :)
>Try looking 2nd hand from abebooks.co.uk
>I've seen it for around £5 here.

Nice one! Christmas all over again if that's the case..... :-)

Thanks again to all. I guess I better test that VCO3 and see if it plays
ball....

cheers,

Dave