[sdiy] CA3130 problem solved ->> S&H problem now

[René Schmitz]

Hi Rutger and all,

I don't know if this has anything to do with your problem, but what I 
find strange about this schematic is the way in which the FET is turned 
on and off. A positive drain will cut off the FET just as a negative 
gate. I'd say that R7 should go to between the output of U1-D and the 
Gate of Q1. Maybe I'd make it a bit larger than 10k.  All that 
offsetting of the input and output would be unnecessary then. Besides 
that the biassing on the input depends on how you couple in the signal, 
if there is a cap on the output of the steering circuit, then its indeed 
Ub/2, if not then it'll be rather something like Ub/3.

Cheers,
  René

Rutger Vlek wrote:
> Haha, no, i didn't miss it. The person who couldn't get it to work was 
> me, i think. And if it wasn't me then i did miss it.
> 
> I have built Ray's Single Chip sample and hold exactly according to the 
> schematic, except for the transistors MPF102. I couldn't find those and 
> replaced then with 2N5486 first and now i've tried the BF245C, but no 
> change... The problem is that my sample & hold doesn't trigger the 
> "hold" transistor right.
> 
> What happens is as follows:
> 
> -When the Sample Rate potmeter is turned completely to the left the CV 
> at the input is directly passed through to the output, without any 
> change (at least, that's what is sounds like. But it's possible that 
> it's resampled with a very high frequency, beyond my hearing capabilities).
> 
> -When i turn the Sample Rate potmeter to the right suddenly the input 
> voltage at that moment is being held at the same level. You could say 
> that the "hold" is now working. But....for an indefinite periode.
> 
> So that's the problem. All components seem to be the right ones, the 
> only difference with Ray's version is the transistors and:
> 
> - two 3M resistors are 3M3 ones (but that shouldn't make the 
> difference). At least in the filter for the clock signal i calculated 
> the frequency difference between 3M3 and 3M and that's really a minor 
> difference.
> 
> - the 200pF clock capacitor (C2) is actually a 220pF. But again...no big 
> difference.
> 
> I'm really stumped, what could cause this problem....
> 
> Regards,
> 
> Rutger
> 
>> From: Ian Fritz <ijfritz at earthlink.net>
>> To: "Rutger Vlek" <rutgervlek at hotmail.com>
>> Subject: Re: [sdiy] CA3130 in Polyfusion Noise module...should a new  
>> one work?
>> Date: Wed, 21 Dec 2005 16:14:11 -0700
>>
>> Did you miss the recent post from someone who could *not* get it to work?
>>
>> At 03:28 PM 12/21/05, you wrote:
>>
>>> Anyway, i'm a happy man now. Next thing is getting the S&H to work. 
>>> But this should be ok since Ray Wilson designed it ;).
>>
>>
> 
> 
> 

-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159