[sdiy] integrator / capacitor leakage

[jhaible at debitel.net]

Hi Rene,

> > I could live with a master clock input, which will then determine the 
> > frequency of the sin and cos outputs. I could just use a PLL to
> > step up from an ordinary VCO signal. Maybe.
> 
> Thats probably more trouble than its worth.

Yes. The more I look at that stuff, the less I like it. Loading
the data into the chip _alone_ frghtens me off. 


> But the PLL "keyword" triggered something in my mind:
> 
> You can use a type 1 (XOR, multiplyer) phase comparator and two
> identical OSCs to make a quadrature signal.
> I saw that in a philips app note a while ago.
> (http://www.semiconductors.philips.com/acrobat/applicationnotes/AN1981.pdf)
> 
> One could do this with two VCOs. The VCOs are arranged in a tracking
> arrangement and the phase comparator would keep both 90degrees
> apart. 

Very interesting! The VCO in the PLL would have two CV inputs then, one
for tracking, and one for the PLL. 

Anyway, I'm _almost_ there with my simple CA3280 + 3 * AD633 setup.
The remaining problem, as I see it, is just the offset variation with
iabc. This is not so bad with CA3280, compared to other OTAs, but could
still be improoved with a discrete solution, SSM2210's for the gm cells,
cheaper pairs for the Gilbert linearisation.

JH.

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