[sdiy] my VCO not oscillating :(

[Michael Ruberto]

>
>Ok, here goes nothing:
>U1 is a standard summing network that scales the inputs to 18mV output
>for 1mV input,

no problem, it's tracking the CV just fine.

I think (experts?).  Check for this first at the top of
>the tempco.  The 1583 will do the exponential conversion sourcing an
>exponential current from the linear (18mV/Octave) input to the base.
>Q1 etc I believe to be high frequency compensation (but this is really
>just a guess).

Q1 seems to be the current converter for the servo loop since it's in the 
feedback path of U2. The HFT adjustment sets the initial level for the error 
signal. I think. Measurments here indicate steady unchanging currents.

    hmm... I'm back to the datasheet for the 4302,

Yes, this also has been a thorn in my side. We had a hunt for it about 6 
months ago and some list members found it's specs but the datasheet itself 
and the pinout are still unknown. I have used this device in a VCF connected 
as DSG viewing the flat side and it works. However, in this application it 
wouldn't make a difference whether I took the signal from the D or S. At 
least I know which is G :)

>FET's operate in enough strange ways I'm really not shure how it will
>act here, wheather we should consider the current out from the mirror
>or the resulting Vce as more important..

Well it looks like an upside-down Mu-amp. It's a source follower but the 
jury is out on whether the bottom FET is contributing to the load or just 
sourcing. I was looking through the archives where they discussed this very 
circuit back in 99 but couldn't find a real conclusion....

There is alot of feedback in
>the circuit after that *scrathes head..*  Experts?
>

By this I am assuming you mean the network comprised of D1, R23, R28 and 
R29? I think that (for lack of better terms) this creates a negative "sump". 
As the sawtooth rises it eventually pokes it's head up enough to reverse 
bias D1 just enough to trip the Schmitt trigger consisting of Q4 and Q5. I 
have been looking rather closely at this portion of the circuit with the 
thought that maybe the "sump" isn't at the right level and the trip never 
happens. On the cathode of D1 I measure an almost perfect -4V and
-3.5 on the anode. Problem is I have no idea what should be here. In this 
situation it would be so helpful if I had some idea of what voltages should 
be present here.

I find that Q5 has .7V on it's base indicating that Q4 is clearly conducting 
but it doesn't seem right considering Q4 sees -3.5V on it's base. With the 
.7 on Q5's base I know it's on and that's verified due to the fact there is 
a steady 15V on the Gate of Q2. Now where I scratch my head is looking back 
at the FET source follower. With 15V on Q2's gate shouldn't Q7 be biased 
off?
With R22 running warm it's obvious that Q7 is conducting. It's like an old 
who-done-it movie. I have several suspicious characters but without knowing 
what clues to look for I may make several false arrests.
Now I know some peeps on this list have built this circuit. Now would be a 
good time for those peeps to chime in before I embarrass myself even further 
;-)

M. A. Ruberto