[sdiy] integrator / capacitor leakage

[jhaible at debitel.net]

When I'm building an integrator for a triangle or sine wave oscillator with an 
amplitude of 20Vpp, I have two options:

a) run the integrator at 20Vpp, or
b) run the integrator at a lower voltage, and amplify the signal
   with an extra amp.

Now, for a certain current into the integrator, the integration capacitor
in case (a) will be much smaller. (Larger voltage to pass in the same time
at th esame current.)

What is better, in terms of precision / leakage?

At first glance, I'd say leakage is mostly leakage _currents_, so
it will be the same in both cases. 
At second glance, I'd say if the leakage currents are not entirely
independent with voltage, case (a) will be worse. 

Is this right? Are there other things to consider?

Background: VCO which not only will run from 0.03 Hz to 20kHz,
but which will also produce very precise waveforms over that
whole range.

Any ideas / hints welcome.

JH.


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