[sdiy] Tim's AvrSynth -- progress, or lack thereof

[Tim Ressel]

Hey,

What was that song? "I fought the emulator, and the
emulator won"?

Ever have a bug covered up by a quirk? That is what I
think I got. The UART receive is not working. I get a
data ready bit, but no interrupt. Also the UCSRC
register kept showing 0x00 (i'm using a jtag-ice).
After much scrating I figured out (i think) that
because the mega16 has this wierd shared register
thing between UCSRC and UBRRH (see page 160 of the
mega16 datasheet), and you have to go through a wierd
timing thing to read those registers, the jtag-ice
probably cannot show the actual values. If i set the
UCSRC bits by hand, i get 3 interrupts from the uart
(data=$FE, which sounds right), but then no more irqs.
Also if I set the UCSRC bits then step the code, the
bits go back to $00. Snarf.

So I think what I have is: my code is trashing the
default values for UCSRC, which is correct, with $00,
which is not(5 data bits .. not!), and the
jtag-ice/mega16 wierdness was masking it. 

So now I am faced with the prospect of finding where
UCSRC gets trashed. Or finding out if my assumptions
are correct.

must.. get.. sleep... (insert sleepy emoticon here)

--TimR


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