[sdiy] ADSR woes..

[Seb Francis]

This is why I love this list :)

Thank you Simon, it works perfectly with R21+C19 bypassed.  Kind of 
obvious now you've pointed it out!

I also removed R45 which is now no longer needed ... I'm always happy 
when a design can be simplified and improved at the same time :))

Seb



simon.oo.o at xs4all.nl wrote:

>Hi Seb,
>
>Try changing R21 and C19 by a jumper.
>
>Then you would have the following states (if I made a mistake, please
>point out)
>
>1) gate low, C9 voltage < threshold: low level at D12 makes -Q=high, as
>U6A output is high as well, Q=low.
>As D7 is not conducting, C9 will be discharged through release pot only.
>
>2) gate low, C9 voltage > threshold: -Q=high, U6a output low, so Q=high.
>C9 will be discharged through both decay and release pot. But this
>situation can only exist very shortly. As soon as C9 voltage < threshold,
>see 1).
>If during this short time the gate becomes high, see 4)
>
>3) gate high, C9 voltage has not reached threshold: as Q was low before,
>it will keep -Q=high.
>C9 is charged via attack pot only.
>
>4) gate high, C9 voltage has reached threshold: Q becomes high, and -Q is
>not kept high anymore.
>C9 is discharged to sustain level via decay pot.
>
>I think this would give you the intended behaviour.
>
>
>Seb Francis zei:
>  
>
>>Hi,
>>
>>I've just finished building my 'NoizBox' and I'm rather disappointed to
>>find that the ADSR part of it is not behaving itself.  Unfortunately I
>>didn't notice this behaviour at the breadboarding stage and now
>>everything is densely packed and soldered onto stripboard :-(
>>
>>This being the case, it's quite difficult to try out different things,
>>so I thought I'd run the problem past the group to see if anyone can see
>>an easy solution ...
>>
>>The circuit:
>>http://burnit.co.uk/sdiy/ADSR.gif
>>
>>The problem:
>>When the release pot VR8 is set to 0 (fastest release) and the envelope
>>voltage at the release point is above a certain level (e.g. depends on
>>Decay and Sustain settings), the flip-flop (U1E, U1F, etc.) doesn't
>>reset reliably when the gate goes low (i.e. when U1:D pin 12 goes low).
>>I'm guessing this is because the current drawn into U1D on release is so
>>high that the output is not square enough to generate a sufficient low
>>blip on the other side of C19 to reset the flip flop.
>>
>>I've tried:
>>Reducing R21 down to 100R
>>Reducing C19 down to 470pF
>>Both these things help (i.e. the envelope voltage at the release point
>>above which things stop working increases, but the problem still exists
>>at extreme settings - e.g. release time = 0, env voltage at release =
>>full)
>>
>>I thought about reducing the values of R21 and C19 even more, but I
>>suspect this still will not be very reliable at extreme settings.  I
>>also though about buffering between U1:D pin 12 and R21 with a voltage
>>follower opamp (e.g. TL082), but this will be a bit messy to do in the
>>board space I have left .. hence over to you guys for your input :)
>>
>>Seb
>>
>>
>>
>>    
>>
>
>
>Vriendelijke groet,
>
>Simon Brouwer
>--> nl.openoffice.org <--
>
>
>
>  
>