[sdiy] Newbie JFET-switch problem

[Richard Arntzen]

Hi Ian!

The needed range is definitely my key problems - I have 0 to 7 in the
design. But - when the diode is replaced with a 1M resistor - won't I get
forward bias of the JFET for the lower voltages..?

I guess my best way out is to scale down the input to 1.5-3 volts, and amp
it back up in the last opAmp. Or I need to get the gate to follow the source
in some way...

Richard

> -----Original Message-----
> From: Ian Fritz [mailto:ijfritz at earthlink.net] 
> Sent: Sunday, August 07, 2005 21:19
> To: Richard Arntzen; synth-diy
> Subject: Re: [sdiy] Newbie JFET-switch problem
> 
> Hi Richard (et al.)
> 
> Looks like perhaps the FET in my circuit has a higher 
> pinchoff voltage than yours.  Also, I use the circuit only up 
> to ~ 4V.  The trouble you are having is most likely due to 
> the diode.  I don't even remember why I put it in -- probably 
> to reduce the amount the gate has to swing.  Try just taking 
> it out or replacing it with a 1M (or so) resistor.
> 
>    Ian
> 
> 
> 
> At 01:22 PM 8/5/05, Richard Arntzen wrote:
> >Hello all.
> >
> >I have built myself a JFET-switch (2N3819) from a schematic kindly 
> >provided by Ian Fritz, and I have some problems. Brief 
> description of the circuit:
> >
> >The JFET base is connected to the anode of a diode (cathode 
> is grounded).
> >Base is also is connected to positive rail (+15V) through a 1.5M 
> >resistor, and to a cap. The basic idea is that:
> >
> >i) Static mode is that the anode of the diode should have a small 
> >positive voltage, and the JFET conducts.
> >
> >ii) when the cap is pulled down (by another part of the 
> circuit), the 
> >base will be pulled down and the JFET will close.
> >
> >iii) The cap will then be slowly charged through the resistor, and 
> >eventually the JFET will conduct again.
> >
> >Now; my problem is with the input range of the switch. I see 
> three modes:
> >
> >A) When the source voltage VS is below 1.19V, it apparently 
> pulls the 
> >gate down. I see an <almost> linear relation between VG 
> (gate voltage) 
> >and VS, up to VS between 1.11 and 1.19V, after which VG 
> flattens out at 
> >0.37V regardless of VS. In this region (VG < 0.37V), the 
> drain voltage 
> >VD is always 0.47V below VS.
> >
> >B) When 1.19V < VS < 3.22V, the JFET is open (VD=VS).
> >
> >C) When VS > 3.22V or thereabout, VD becomes <almost> constant at 
> >3.26-3.3V regardless of VS.
> >
> >Having done some reading I see that C) happends because of 
> saturation.
> >Question 1: is 3.3V a normal saturation limit for the 
> 2N3819? Can't see 
> >it from the datasheet (at least, I can't).
> >
> >A) I don't understand - is this due to the threshold 
> voltage? Why does 
> >the JFET conduct anyway (with a constant resistance?), and 
> why does it 
> >pull current from the base?
> >
> >And finally; how do I fix this? Do I have to scale the 
> source voltage 
> >to be between 1.2 and 3.2V? Does these JFET parameters vary, and how 
> >can I get this information from a datasheet?
> >
> >Hoping for some help from the experts,
> >
> >Richard
> 
>