[sdiy] Verilog Uart Done

[David Panseri]

I agree. At my college they had us use FPGA Advantage for processor
design in VHDL. Granted, it makes life alot easier but you don't
really learn much of the language using it. I picked up a book and
read up on the basics of VHDL on the side. It came in handy the next
semester when I was doing a project for my embedded systems course and
needed to write some custom decoders and such.

Question: Where did you get the FPGA board/software you are using?

-Dave Panseri

On 4/17/05, James Patchell <patchell at cox.net> wrote:
> Nope, writing it all by hand.  That is the only way to really learn it...
> 
> At 10:18 PM 4/17/2005 -0400, David Panseri wrote:
> >That is quite impressive, especial the softcore processor!  Are you
> >writing all the code by hand or are you using something similar to
> >FPGA Advantage?
> >
> >-Dave Panseri
> >
> >On 4/17/05, James Patchell <patchell at cox.net> wrote:
> > > I just got the Uart Reciever done now as well.  Both peices of code can be
> > > found at:
> > >
> > > http://www.oldcrows.net/~patchell/IpArchive/HdlArchive.html#Uart_Softcore
> > >
> > >          -Jim
> > > ***************************************************************
> > > http://www.oldcrows.net/~patchell
> > >
> > > ***************************************************************
> > >
> > >
> 
>          -Jim
> ***************************************************************
> http://www.oldcrows.net/~patchell
> 
> ***************************************************************
> 
>