[sdiy] digital synth design.

[ChristianH]

On Wed, 27 Oct 2004 15:51:19 +0200 (CEST) Rainer Buchty wrote:

> >I think software isn't that much of a problem (unless you are a pure
> >hardware man) - as long as the patch structure doesn't involve much
> >synthesizing and processing, i.e. mostly sample playback.
> 
> Ah, but here the fun starts already:
> 
> (1) raw wave parameters
> - original tuning
> - start position
> - end position/length
> - loop point (if not "sample end=loop end")
> - multisample zones (you don't want to play that 512-byte SAWUP sample 
>   all the way up to key 127)

Ok, all in all this surely isn't a trivial project, but it looks as if
there's nothing really impossible in it. And you're right, it really
could be fun :-)

> (2) patch parameters
> - selected waveform(s)
> - coarse tune (octave/semitones)
> - fine tune (cents)
> - pitch modulation (pitch bend, pitch EG, pitch LFO, maybe eben audio-FM 
>   from a second osc) and amount
> - one-shot vs. looped playback (not to mention forward/backward looping)
> - hard-sync (for multi-osc voices)
> - address resolution
> 
> At a later stage, amplifier and filter -- synthesizing and processing --
> will contribute even more mess for example, the program control block of
> ESQ1 and SQ80, i.e. their patch parameters, are 102 bytes per sound.
> 
> This includes 3 oscillators, 4 EGs, 3 LFOs, 3 DCAs, VCF, final VCA and
> panning plus some additional control stuff (sync, AM,
> splitting/layering, envelope mode, oscillator restart, voice reuse, mono
> mode, portamento) including the necessary modulation routing (source &
> amount).

Well, that's what I separated from the basic sample playback part, as
kind of an encore. Mostly dispensible for pure sample playing, but of
course nice to have.

> Next question is if you want to burden all playback onto the processor,
> or if the processor only becomes master control where playback is done
> by either a (bunch of) slave processor(s) or some dedicated hardware
> circuitry (counters clocked with variable frequency or phase
> accumulators).
> 
> And, while doing this, consider introducing interpolation to avoid 
> nastily squeaking phase-accu based oscillators.

Utilizing a software approach, that's what I'd do anyway, using a fixed
output sample rate and transforming the time coordinate into a sample
readout offset. 
AFAIK, early hardware samplers like the Fairlight always read the memory
samples sequentially word by word and transposed into variable output
rates, using variable clock frequencies.

Bottom line is - it may be feasible in theory, but having a day time
job and not doing sdiy full time, the total project would probably take
prohibitively long to complete. But, it's not that I never did sketchy
considerations how to make a sampler... <gr>

Christian