[sdiy] Radfio Shack

[Rainer Buchty]

>I seem to remember reading something about using more than two 6502 CPUs,
>along with a multiphase clock. Does anyone else remember that? I think it
>takes a bit of additional support circuitry, unlike the trick with the
>2-phase clock, which requires almost no additional circuitry.

Hm. Following the 6502 datasheet all you need to care about is the
falling edge of phi2; whenever that occurs, a memory access becomes
effective.

So if bus drivers and memory are fast enough (assuming the 6502s will be
happy about the asymmetrical clock, but since they are fully static they
shouldn't care as long as the pulses are adhere to minimal low/high
times), you could e.g. use an 8-times clock, drive a 2-bit counter and
use the counter's output with a 2:4 decoder delivering 4 sequential
clocks:

Access	 * * * *
CPU #1	--______
CPU #2	__--____
CPU #3	____--__
CPU #4	______--

However, assuming that each pulse is alrady at maximum clock frequency,
you don't gain any speed-up compared to the 2-CPU solution, but only
distribute work-load among the 2x2 CPUs.

You probably could mingle the clock cycles in an overlapping way by
adhering to both, t(PWL)/t(PWH) and minimal hold/delay times. Not sure
if you'd really gain anything, though, maybe 10ns out of t(PWH)-t(MDS).
So instead of a 2-phase a 3-phase clocking might be possible.

Haven't seen it so far, but would definitely be interested in schematics
showing auch clocking.

Rainer