[sdiy] Pcb design question

[Bert Schiettecatte]

Hi list,
 
I'm working on a pcb design and I have some questions about traces.. 
 
I have an SRAM connected to a microcontroller. There is an 
octal latch between the sram and the mcu, and the data traces 
go from the SRAM to the latch, and continue onto a 10-pin 
header, and then continue over the upper layer to the mcu. 
Note that the traces sort of form an inductor, with in the 
core/center a GND via/plane. I am close to finishing this PCB 
and I'm starting to worry about a lot of things. One of my 
worries is that these data traces forming a loop/inductor 
could inject a lot of noise into the GND net. Am I correct? 
Or am I worrying to much?
  
You can have a look at a close up of the problem here:

http://www-ccrma.stanford.edu/~bschiett/pcb.jpg


Thanks,
Bert