[sdiy] Newbie question regarding the 4069 VCO

[James Howe]

Thanks for the extra description.  It has helped clear up some of my  
questions concerning this VCO.  I have a couple followup questions which  
I've embedded in the text below:

On Tue, 09 Nov 2004 01:22:56 +0100, René Schmitz <uzs159 at uni-bonn.de>  
wrote:

> Hi James,
>
> James Howe wrote:
>
>> To that end I've been studying the 4069 VCO found at   
>> http://www.uni-bonn.de/~uzs159/vco4069.html and reading the various   
>> e-mails sent to this list concerning how it works.  [...]
>
> Well, lets start with the input stage (the question in your private  
> mail...).
>
> [...]
>
> How the individual CVs is summed, can be understood if you consider that  
> the upper leg of the divider is much larger than the lower, and that the  
> base draws very little current. [...] That means you can view this node  
> as roughly a current summing node.
>

I think I understand this.  I remember reading that a simple current  
source is just a voltage and a resistor as long as the input voltage is  
substantially larger than the load voltage.  I guess this holds true  
because the voltage at the transitor is quite small relative to the  
control voltages?

>
> For the exponential convertor, I recommend to read my expo tutorial. It  
> doesn't cover this special circuit. The math however does apply as well.  
> (A few signs will change, but the general concept is the same.)
>

I've read through it once, and I expect I'll reread it a few more times,  
but I think I understand what is going on here.

> The integrator behaves the same as the textbook version with an opamp.  
> Just think of the invertor as an opamp running on single supplies, with  
> its + input tied to Vb/2. The invertor input being the - terminal.
>

Ok, this I don't quite understand.  I think I'm hung up on how an invertor  
works and I'm not taking into account other things, but here is what I  
don't get.  From my reading on how an invertor operates, it takes an input  
voltage, and if the voltage is 'low', the output is 'high' and if the  
input is 'high', the output is 'low'.  I think of 'low' as 0v and 'high'  
as +V where V is the value of the positive rail (I think I'm using the  
correct terminology).  If this is the case, how does this integrator  
circuit produce a voltage ramp?


> The specialty here is the way how the integrator gets reset. Normally  
> you would have a switch (BJT FET or the like) to short the cap  
> terminals, and discharging it. Here we push current into the invertor  
> summing node, forcing the integrator to work into the other direction.
> The diode current and the expo current have opposite direction.

I'm a little fuzzy on this operation.  When you talk about the 'diode  
current', is this the top diode, or the one which is parallel to the  
680ohm resistor?  Is the summing node the capacitor/diode/resistor portion  
of the circuit?

> The extra resistor in series with the cap is a so called franco  
> compensation resistor. Its purpose is to compensate the finite reset  
> time of the VCO. Resulting in better high frequency response.
> Its action is that the expo current generates a voltage drop across it,  
> so that the schmitt trigger sees a slightly higher voltage than that of  
> the cap. So the higher the current, the earlier the schmitt trigger  
> fires. "Earlier" in both timing and voltage sense. Dimensioning is  
> Rcomp*C =t(reset). The diode is necessary to bypass the resistor during  
> the reset portion of the cycle, so that the resistor is only in effect  
> during the ramp portion of the wave.
>

I think I understand most of this.

>
> The schmitt trigger can be understood by considering that the decision  
> threshold of the gate input is halfway between the supply. The voltage  
> of that node is dependant on both the input, and the state of the  
> schmitt triggers output. When the transition region is approached, the  
> moving output moves the node voltage into the direction of change that  
> is due to the input voltage. This is positive feedback. (Sort of like  
> the spring action on a microswitch.) So there is a region where the  
> output state is dependant on the previous state.
> It can be best understood if you calculate the voltages at the input  
> node for various input voltage combinations. Its a voltage divider  
> again. (Ok, to really explain it, I would need to make an  
> asciimatic-animation...)
>

I need to ponder this one some more and actually try calculating some  
voltages.

> [...]
> The dimensioning of the input divider has the same considerations, also  
> the NTCs only come in E6 or E12 values, so that limits the choices. I  
> wanted to stay close to 100k, since thats considered the standard input  
> impedance. But somewhere near 20 or 50k would work as well.
>

Ok, I didn't know that 100k was considered a standard input impedence so  
the selection of resistors at this point makes sense now.

> Hope this helps.

It has helped considerably.  Still a ways for me to go, however.  Thanks  
for answering what must be really simple questions.

Thanks again.


-- 
James Howe

Contact: http://public.xdi.org/=James.Howe