[sdiy] lookup table as expo converter

[Magnus Danielson]

From: ASSI <Stromeko at compuserve.de>
Subject: Re: [sdiy] lookup table as expo converter
Date: Tue, 25 May 2004 00:00:40 +0200
Message-ID: <04052500004001.00645 at Robert>

> On Monday 24 May 2004 20:24, Paul Schreiber wrote:
> > MOTM-520 Cloud VCO does use a look-up table for the expo converter
> > (16-bit, 64K entries!)
> 
> This seems wasteful unless you do something else (like nonlinearity 
> correction) with that lookup table at the same time.

Actually, a 65536 entries of 16 bit each is just 4Mb or 512kB memory. Those are
fairly cheap these days. If you are going to do *any* processing in addition
to a smaller lookup-table you need to have it really minimalistic processing or
it is more expensive. That is if you do it in physical hardware. For FPGAs
there are so many tricks to play that it is really booring. If you use RAM, you
just calculate the table in software. Things have changed alot, transistors get
cheaper every year. Unfortunately, with that the skill of clever design in
small counts of components is less needed and thus less called for.

>  You can split the 
> linear code, convert the MS part with a first DAC and feed the 
> resulting CV into the multiplying input of another DAC handling the LS 
> part. Further compression of the table can be achieved by interpolation 
> via d/dx 2^x = 2^x ln2. Some constants can be folded into the reference 
> of the multiplying DAC to further simplify the lookup. Since 2^x is a 
> simple n:1 decoding function, you may never need an actual lookup table 
> or at least not a very large one.

CORDIC anyone? ;O)

Cheers,
Magnus