[sdiy] AHDSR schemo

[Rainer Buchty]

> Just a naive suggestion : why don't you use a similar solution
> as the part of the schematic producing the sustain segment ?
> Then your module becomes ASDSR...

S? I'd rather have thought of R together with a comparator:

After the attack phase, the hold phase is entered. The hold time is the
initial value of this release stage. As long as the output is not zero, we
just output 100% level. If zero is reached, the EG advances to the decay
stage.

Cheating, but probably much simpler, would be to create a digital envelope
generator around a PIC, AVR or whatever. That way you could do arbitrary
envelope shapes using the level/rate model.

Rainer