_[sdiy]_ICL8038 worst ic off all time!

[Scott Gravenhorst]

The output (pin 3) is a bipolar TTL arrangement.  For increased switching
speed, both totem pole transistors are on for an instant causing a nasty
current spike.  This can cause soft synch problems for VCOs.  The 7555 is pin
for pin compatible, but is CMOS, so you don't suffer the current spike during
output state transistions.  It's a fix for soft synch problems with a PAiA
FatMan which comes with bipolar 555 VCOs.

"J. Larry Hendry" <jlarryh at iquest.net> wrote:
>----- Original Message -----
>From: Scott Gravenhorst <music.maker at gte.net>
>555, I agree, in fact, I'd put that on the "worst IC of all time" list.
>
>Why?  I have an analog shift register that requires an external clock.  I
>was considering adding a dual clock using 555 timer circuits (actually a 556
>dual IC) to provide a variable clock.  What is so bad about this chip?
>There are many circuits out there showing it as a nice variable clock.  I'm
>not trying to make a VCO out of it. :)
>
>Thanks
>Larry Hendry
>
>
>
>

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