[sdiy] oscillator jitter / phase noise

[Magnus Danielson]

From: "Czech Martin" <Martin.Czech at Micronas.com>
Subject: RE: [sdiy] oscillator jitter / phase noise
Date: Mon, 7 Jun 2004 16:23:12 +0200
Message-ID: <D9D56E8FA1A73542BE9A5EC7E35D37FFF390A8 at EXCHANGE2.Micronas.com>

Dear Martin,

> Well, cold or not cold, a quartz stabilised DCO will certainly have less
> jitter and verly low long term drift.

Indeed, indeed.

> In the case of a single vco it should make no difference.
> Even the old circuit sare not that bad, they were no
> intended as random generators, after all.
> 
> I think that the difference will only be audible
> if two or more oscillators beat against each other.

That might be debated, and I'd love to hear the comments!

> DCOs tend to have very regular beating patterns,
> but free running vcos tend to have complex phasing
> patterns due to their drift. This seems to be a good
> deal of the beauty.

I agree. It really seems like that.

> Perhaps this implies also the measuring method:
> 
> compare a quartz oscillator with some vco.
> There are circuits to compare the phase difference, i.e. they put out a low
> frequency signal. As long as the acumulated phase difference is only less
> than a cycle, this will work. In practise it will be off and running, but
> there are phase comparators which can deal with that, too.
> Perhaps a simple way to do the measurement.

The frequency difference between the oscillators will be a problem unless you
can handle it. In practice, this is what a time interval measurement will do
for you, since it is nothing else than a phase comparator.

Using a Phased Locked Loop to lock either oscillator to the other is another
no-no, since that will alter that oscillators phase modulation characteristics.
You can do that when you know that you only alter the part of the phase-noise
that isn't of interest. When you do that, you can use the phase detectors
output for the phase comparision, since it is already doing that task. This is
BTW a classic way to measure jitter. The PLL's bandwidth will also form the
-3dB point of the highpass filter for the phase-comparator's response. Below
that the PLL is tracking and thus the phase differences is dampened out.
That's all fine and dandy, but we want to examine the phase-noise way down
there, and then will the PLL bandwidth requirement be a problem. Also, we can
easilly do better, so let's do that.

> Using one of those HP jitter analyser boxes is certainly more straight
> forward, the problem is that people who have access to such
> an expensive machine have perhaps no access to vintage gear.

I have one at work, knows how to operate it and the vintage gear keeps growing
on me. ;O)

> Anyway, using a reference frequency in this way will take away the high
> bandwidth problems which the direct pulse with measurement certainly has
> (logging the data for every cycle).

Logging each cycle's period isn't a huge problem, sampling in high speed
enought to later be able to retreive the cycle period with high enought
accuracy is.

Cheers,
Magnus