[sdiy] Re: VCO reset time for BBD-based PM

[JH.]

> > I think my storm tide flanger clock VCO goes over 1MHz, but it's ben
some
> > time since I
> > measured it. Tracking is not overly good, though, and it does need some
> > hefty HF compensation.
> > http://home.debitel.net/user/jhaible/jh_storm_tide_1.pdf
>
> Shouldn't Q4s collector be tied to a negative supply? I would be worried
> about getting into the saturation region in that emitter follower.

No, that's the old ARP expo converter - it works just fine. Vce_sat is
somewhere
around 200mV, and Vbe is certainly always higher even for the tinyest
colletor current.


> And I must say I don't see how R14 would affect the switching threshold
> of the gate.

It doesnt. That was my mistake in my previous mail: The is no HF
compensation
in this circuit. (I should have looked at my own schemos instead of speaking
from
memory.) So that should be "it *could* need some HF compensation".
As it is, it tracks over 2 octaves maybe. I certainly should add HF
correction
and see how far I'll get.

Now R14 serves an entirely different purpose:

> Wouldn't this only slightly increase the impedance of your
> current source?

Well that's the job of J1, forming a cascode output together with Q2, which
should make the current output more ideal, i.e. increasing its output
impedance.
Now R14 is used to set an upper limit for the clock frequency without
compromising the expo function nor the output impedance.
The benefit of using a FET for the cascode (other than no Gate current
will take away from Q2's output current) is that the gate can be tied to GND
while the source will cut off the drain current when the source is going
above a certain
positive voltage. (*Here* this is needed to keep Q2 from saturating!)

It's quite confusing to see three transistors that form a signal chain, with
one collector, one emitter and one gate hardwired to GND, but
it actually works. (;->)

JH.