[sdiy] VCO reset time

[Scott Bernardi]

The compliance of the current source/sink comes into play then. You'd 
have to have a different topology. For example, most expo converters 
have the transistor pair bases referenced to ground.  In an npn current 
sink, pulling current out of the integrator capacitor would cause the 
voltage to ramp negative - but that would saturate the expo transistor. 
You'd have to reference the transistor base to some negative value 
greater than the sawtooth peak.

JH. wrote:

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>A simple FET source follower will do. No need to build an active integrator.
>Drawback: expo converter will not work into a virtual GND node anymore.
>(Does this matter?)
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>JH.
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