[sdiy] MOSFET ANGST

[rizacan]

Hi

As far as know for NMOS transistor must work in thriode region (Vds < 
Vgs-VT ) in order  to  use as VCR

In thriode region (Vds < Vgs-VT ) the output current is
Id=B[(Vgs-VT)Vds+(Vds)^2/2]                                 (1)

For very low Vds (1) gives                                          
Id=B[(Vgs-VT)Vds]
and  then  Rds=1/(B(Vgs-VT))

Vds, Drain-Source voltage. VT, Tresholt  voltage and B conductance , 

Cheers

Scott Gravenhorst wrote:

>I have started doing a few experiments, simple stuff just to see if what is
>supposed to happen actually does.  So I built a little voltage controlled
>attenuator.  It sort of works...  read on.
>
>Please see http://home1.gte.net/res0658s/MOSFET_test.gif
>
>In all cases, the AC input is a triangle waveform from a signal generator.
>
>I started with "A" and noted what I would call unkindly behavior.  At zero
>gate volts, the output is "full scale" and looks like a proper triangle
>waveform.  However, as I increased the gate voltage, generally, the
>amplitude of the output was attenuated as expected, but there is
>assymetrical distortion.  I looks like as the gate voltage increases, the
>negative portion starts to soft clip _first_, then after the voltage
>increases more, the positive portion begins to drop in amplitude, but no
>soft clipping occurs!
>
>Ok, so I thought perhaps I needed to do experiment "B", which uses both the
>P and the N transistors.  Guess what...  No difference, meaning that as the
>gate voltage increases, there is attenuation, but the signal is still
>asymmetrically distorted.  I also tried reversing the drain and source
>connections of the P transistor - no difference.
>
>WARNING: THIS MAY PROBABLY BE POORLY WORDED, NON-EE LANGUAGE.
>I got suspicious that the P transistor wasn't doing anything because it
>appears to me to be reverse biased, i.e., in normal inverter use, it's
>source is more positive than it's drain and the more negative the gate is
>with respect to it's source, the less it conducts.  It looks like both the
>N and P MOSFETs are depletion mode, (I can't find this in the datasheet)
>but the fact that they are opposite types (N vs P) means they work opposite
>and make a nice inverter with 2 transistors.
>
>Anyway, I did experiment "C" and found no change in output at all as gate
>voltage increases.  As in nothing happens when I turn the knob.  To my way
>of seeing it, this means that the idea of folding a 4069UB (i.e.,
>connecting pin 14 to pin 7) has no advantage because the P transistors
>won't do anything for us.
>
>I'm looking for pointers, explanations, etc., like "HEY SCOTT, YOU
>BONEHEAD, YOU NEED TO CONNECT THE FRAMUS TO THE PHLORBIS THROUGH A
>HYPERSPACE MULTIZORCH!".
>
>Is this kind of asymmetrical distortion expected?  If not, how the héll do
>I fix it?  I thought that using such a low input would be wonderful...  Ok,
>I tried reducing the input voltage to 40 millivolts, it looks better, but
>still asymmetrical.
>
>Help???
>
>
>
>
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