Betreff: RE: [sdiy] Re: 4049 and 4069

[jhaible at debitel.net]

>I guess it is the normal CMOS disease:
>1/f noise, and the corner sitting at 100kHz [...]
>In fact, CMOS logic gates can be used as noise
>source (linear, not time discrete shift registers).

Interesting! So this is a pink noise source without the need
for a 3dB/Oct filter then ?

>You can see them on my web site.
http://www.geocities.com/SoHo/Museum/4459/circuits/cmosnoise.html

Can't get there right now. I'll try it again later.

>JFETs behave a little better, since no oxide
>isolation. The basic Id/Ug characteristic is similar,
>so why not building a distortion element with JFETs?

This is certainly possible, but also quite complicated. Trimpots
or component selection needed for setting the right bias point,
because of component tolerances.

And even if you have two matched complementary JFETs (not
easy), you still have to bias them with extra voltages <Vss
and >Vdd is you want to get that simple inverting amp
gain block of a CMOS chip that is "self biasing":
A single stage CMOS inverter will only draw current for
a certain range of input voltages _between_ Vdd and Vss.
With JFETs, you'd have to go bejond the rails to turn them off.

(OTOH, you can make a nice _noninverting_ unity gain
buffer from two complementary JFETs, as Don Tillman
has shown some time ago.)

So yes, one can surely use JFETs to make good distortion
functions, but it takes some effort.

The great feature about the CMOS inverters is that they 
act as a sort-of inverting opamp, with the soft clipping
function alreasy built-in, without any extra circuitry.
(Just the feedback resistor for DC biasing, as with any 
opamp.)

So it _would_ be interesting to have something like a
low noise 4069, integrated or built from discrete
transistors.

Are _all_ MOSFETs so bad, noise-wise?

JH.



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