[sdiy] Mismatch in word length with I2S (16/24 bits), it won't work ?

[Ingo Debus]

Am Freitag, 13.02.04 um 16:34 Uhr schrieb Jay Schwichtenberg:

> I2S is a 'bus' designed to pass converter data around. It consists of 
> a word clock, bit or data clock and data. There is usually a 256x, 
> 384X or 512X master clock used to provide internal clocking to the 
> converter too. I don't know if that is part of the I2S spec. You might 
> want to grab something like the Crystal CS4390 or some other data 
> sheet and take a look at it. What most people don't know is there is a 
> spec (connector & drivers/receivers) for running the I2S signals in 
> parallel between seperate devices. We usually use SPDIF or AES/EBU or 
> light pipe because it is different.
>

I'm wondering if this is the bus used by the mysterious HD62098 I 
mentioned recently. The input pins are called "Master Clock Input" 
(CLKIN), "Synch. Signal Input" (SYWIN) and "MEL formatted signal input" 
(IMEL0...IMEL3). Does anybody know? What does MEL stand for?

Ingo