[sdiy] re: interesting digital circuits

[tuj]

Wow, is my math that bad?  I understood this chip to be 1Mb of addresses, 
each holding16 bits of data, or 2Mb of addresses, each with 8 bits.  1Mb = 
2^20 = 1,048,576 samples / 44100 = 23.77 sec.  Right?  I'll encode the left 
channel as the 8msb's and the right as the 8lsb's.  As for the ADC/DAC, I'm 
going with 8-bit units that have parallel inputs/output to make things simpler.

The interpolation idea is pretty cool, but I think it would get pretty 
complex to do more than just a single interpretation between 
samples.  Unless someone has a clever design for this?  I'm not sure how to 
do multiple steps between samples without bringing division into play.  If 
I do that, I'll have to implement more complex timing so I can accomplish 
all the ops between read/writes, plus buffers, plus multiple 
ALU's.  Although I suppose right-shifts followed by an add would give a 
reasonable approximation.  As you can see by my selection of an 8bit ADC, 
this isn't intended to be hi-fi.  More of a learning experience.

Thoughts?  Thanks Paul + Richard for your input.
-tuj

At 05:06 AM 12/15/2004, Paul Maddox wrote:

>This equates to a 20Khz sample rate and only 10Khz of bandwidth..
>
>Thats it, its quite simple, but 1Mbyte won't give you 48seconds at 44.1Khz
>sample rate, sorry.
>I built a simple one using a 64Kbyte SRAM and 8bit ADC/DAC, it worked, the
>feedback I did with analogue circuitry.
>
> > Thoughts?  Is there a need for the reads/writes to be buffered?
>
>nope, just need an Output Enable pin on the ADC and  WRITE pin on the DAC,
>like this ;-
>
>Put SRAM into READ mode.
>enable DAC write line,
>Disable DAC write line
>Enable ADC output
>put SRAM into write mode.
>Disable ADC output.
>
>I would also suggest that you 'clock' the ADC each time you finish reading
>it, this ensures that the ADC output is stable whilst writing to the SRAM.
>
> > I've also thought about incorporating two shift registers, so that on a
>write, the existing value in memory, and the new value from the ADC will
>each go into a shift register, shift one bit right, then both shift
>registers feed an adder, which yields the result to put back in memory.
>Number of "repeats" could be controls by the magnitude of the right shift on
>the value coming out of memory.
> >
>
>too cmoplex for me, as I said, I just did it the easy way.
>
> > Anyone actually done this?  Any advice would be appreciated.  Thanks!
>
>The hardest part you're going to face is finding compatible 16bit ADC and
>DAC that use parallel data.
>most are seiral, so you'll need to convert from serial to Parallel to use
>you SRAM (assuming you're using parallel SRAM and not serial).
>
>Paul