[sdiy] re: interesting digital circuits

[Paul Maddox]

Tuj,

> Well, I'm thinking about building a digital delay.  I'm looking at using a
BS616LV1622 SRAM chip.  Its 1MBx16 bits or 2MBx8 bits, switchable.  Seems
like that should give me about 48 seconds of mono delay, or about 24 seconds
of stereo delay.
>

This equates to a 20Khz sample rate and only 10Khz of bandwidth..

> Does anyone have any other RAM chips that they like?  I'm certainly no
expert.  Is there a recommended memory controller chip?
>

why?
its only SRAM, you don't need to refresh it.

> Maybe I'm missing something, but this seems relatively straight-foward.
Store a write address and a read address in two counters.  Set up the
counters to wrap at the end of the address range.  Initialize the counters a
certain range apart to set the delay time (probably at 0x0 and 0xMAX).
Increment the counters on a clock osc, set at 44.1kHz should yield CD
quality sound.  varying the speed of the osc. should be an easy way to
increase/decrease delay time.  Each clock reads the memory location, sends
value to DAC, reads current value at the ADC and writes it to memory.
>

Thats it, its quite simple, but 1Mbyte won't give you 48seconds at 44.1Khz
sample rate, sorry.
I built a simple one using a 64Kbyte SRAM and 8bit ADC/DAC, it worked, the
feedback I did with analogue circuitry.

> Thoughts?  Is there a need for the reads/writes to be buffered?

nope, just need an Output Enable pin on the ADC and  WRITE pin on the DAC,
like this ;-

Put SRAM into READ mode.
enable DAC write line,
Disable DAC write line
Enable ADC output
put SRAM into write mode.
Disable ADC output.

I would also suggest that you 'clock' the ADC each time you finish reading
it, this ensures that the ADC output is stable whilst writing to the SRAM.

> I've also thought about incorporating two shift registers, so that on a
write, the existing value in memory, and the new value from the ADC will
each go into a shift register, shift one bit right, then both shift
registers feed an adder, which yields the result to put back in memory.
Number of "repeats" could be controls by the magnitude of the right shift on
the value coming out of memory.
>

too cmoplex for me, as I said, I just did it the easy way.

> Anyone actually done this?  Any advice would be appreciated.  Thanks!

The hardest part you're going to face is finding compatible 16bit ADC and
DAC that use parallel data.
most are seiral, so you'll need to convert from serial to Parallel to use
you SRAM (assuming you're using parallel SRAM and not serial).

Paul