[sdiy] samp. freq for ADSR ?

[mark verbos]

In the Buchla 257 "math module" , control voltage processor, the clock 
runs at 21kHz
I'd say that's generous for CVs.

The Buchla 248 Multiple Arbitrary Function Generator has a master clock 
of 256k, devided by 2 for the main clock. Then every cycle clocks 
through 8 bits for 32 steps, from a 256 step shift register. Creating a 
500Hz sampling frequency. Nyquist's theory is that the maximum sampled 
frequency is half the sample rate, leaving the Buchla MARF with a 
maximum of 250Hz (real low for audio). It seems too low to me, 
especially when you're talking about LFOs.

Somewhere in between those 2 seems about right.

Mark



>----- Original Message ----- 
>From: "jbv" <jbv.silences at Club-Internet.fr>
>To: <synth-diy at dropmix.xs4all.nl>
>Sent: Friday, April 02, 2004 10:09 AM
>Subject: [sdiy] samp. freq for ADSR ?
>
>
>  
>
>>Hi all,
>>
>>OK, 48 KHz is a theorically fine sampling freq for audio signals.
>>But right now I'm brainstorming on a project in which multiple
>>ADSR signals would be generated by a uC / DAC / S&H.
>>What is the optimal freq at which each signal should be refreshed /
>>incremented ?
>>At first glance 48 KHz seems a luxury, but what about very fast
>>AD ?
>>
>>Thanks,
>>JB
>>
>>    
>>
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